The present invention relates generally to hybrid microcircuit packaging, and more particularly to a low temperature cofired ceramic package for use with microwave and millimeter wave gallium arsenide integrated circuits, and the like.
The current state of the art in packaging microwave and millimeter wave gallium arsenide integrated circuits involves inherently complex structures designed to meet radio frequency, thermal and reliability requirements of microwave products. These packages are expensive and are typically assemblies of piece parts. Typical of these assemblies are packages which employ (1) metal bases and sidewalls with glassed in feedthroughs, (2) metal or ceramic bases with metal sidewalls and brazed ceramic feedthroughs, (3) ceramic bases with epoxied ceramic covers, or (4) metal bases with glassed on ceramic covers. An article entitled "Next-Generation High-Speed Packaging," by Gary Holz, published in Microwave Systems News, in the January, 1988 issue examines some considerations in package design for high speed applications.
Currently available packaging schemes are generally complicated structures which employ a combination of ceramics, metals, glasses, solders, mixed this and thick film technologies with complicated input and output leads structures. Much of the expense of such conventional packages is related to multiple-step, labor-intensive assembly procedures. Radio frequency (RF) performance is also degraded in most conventional packaging designs due to discrete elements, such as resistors, capacitors, couplers and matching networks, and the like, added to the package.
In conventional packaging schemes, semiconductors, passive components and microwave integrated circuit chips, including gallium arsenide chips, are attached to substrates or metal portions with conductive adhesives, or the like. Although some high power chips are eutectic mounted for thermal performance, alternate techniques are often used because of the difficulty of eutectic die attachment which often damages the thin, brittle gallium arsenide integrated circuits.
Metal box type assemblies are generally tightly packed with individual substrates and passive chip components that are mounted with either conductive or nonconductive adhesives and interconnected with bonded gold wires or ribbons. It has been determined that manufacturing yields for such assemblies are low due to the incorporation of electrically faulty chips, or to mechanical problems encountered in manual assembly of numerous small components and fine wires in a precision assembly. RF and DC hermetic feedthroughs in these metal-walled enclosures are generally soldered, brazed, or glass sealed coaxial assemblies. Although currently available infrared tunnel oven and induction curing methods have been successful in manufacturing such assemblies, electrical feedthroughs employed therein are prone to insulator damage, and connection rework frequently damages other costly components. Rework is frequently a progressively degrading process, as one repair may require removal of, or cause damage to, previously operational parts.
The development and use of low temperature cofireable ceramics has been discussed in the literature over the past 4-5 years. See, for example, "Development of a Low Temperature Cofired Multilayer Ceramic Technology," by William A., Vitriol et al, 1983 ISHM Proceedings, pages 593-598, "Electronic Packaging Using Low Temperature Co-Firable Ceramics," by A. L. Eustice et al, Hybrid Circuit Technology, pages 9-14, June 1987, "A New Low Temperature Fireable Ag Multilayer Ceramic Substrate Having Post-fired Cu Conductor (LFC-2)," by S. Nishigaki et al, 1986 ISHM Proceedings, pages 429-449, "Low Firing Temperature Multilayer Glass-Ceramic Substrate," by Y. Shimada et al, Proceedings 33rd electronic components Conference, (1983), pages 314-319, and "Co-fired Ceramic Multilayers: When Reliability Counts," by R. Keeler, Electronic Packaging and Production, May 1987, pages 40-42. The low temperature cofireable ceramic technology provides the advantages of fine conductor and via geometries and fewer processing steps compared to comparable thick film multilayer technology, which has the advantages of low resistivity conductor materials and resistor material compatibility.